ELECTRONICS PROJECTS

VLSI Projects

VLSI Projects are excellent for ECE final year students pursuing BTech, BE, MTech, or ME degrees. These projects allow students to gain practical experience and showcase their skills to project guide through proper documentation, plagiarism-free reports, and source code.

Artificial Intelligence AI

VLSI Projects List

Here the list of Popular VLSI (VHDL / Verilog) projects include .

View All Projects
S.NOIEEE PROJECT TITLESTECHNOLOGY
AP4VL01BINARY TO GRAY CODE CONVERTER IMPLEMENTATION USING QCAFront End
AP4VL02Design of a Reversible Floating-Point Square Root Using ModiÞed Non Restoring AlgorithmFront End
AP4VL03Design and Verification of DDR SDRAM Memory Controller Using System Verilog For Higher CoverageFront End
AP4VL04Concurrent Error Detectable Carry Select Adder with Easy TestabilityFront End
AP4VL05The Mesochronous Dual-Clock FIFO BufferFront End
AP4VL06A High-Performance Multiply-Accumulate Unit by Integrating Additions and Accumulations into Partial Product Reduction ProcessFront End
AP4VL07Energy-EfÞcient Low-Latency Signed Multiplier for FPGA-based Hardware AcceleratorsFront End
AP4VL08An EfÞcient Parallel DA-Based Fixed-Width Design for Approximate Inner-Product ComputationFront End
AP4VL09Design of Power EfÞcient Posit MultiplierFront End
AP4VL10Design and analysis of High speed Wallace tree multiplier using parallel prefix adders for VLSI circuit designs.Front End
AP4VL11EfÞcient Design for Fixed-Width Adder-TreeFront End
AP4VL12Hardware-EfÞcient Post-processing Architectures for True Random Number GeneratorsFront End
AP4VL13Chaos-Based Bitwise Dynamical Pseudorandom Number Generator on FPGAFront End
AP4VL14Low-Power Approximate Unsigned Multipliers With ConÞgurable Error RecoveryFront End
AP4VL15Implementation of Ripple Carry and Carry Skip Adders with Speed and Area EfficientFront End
AP4VL16Borrow Select Subtractor for Low Power and Area EfficiencyFront End
AP4VL17Rapid Balise Telegram Decoder with Modified LFSR Architecture for Train Protection SystemsFront End
AP4VL18A Low-Power Yet High-Speed Configurable Adder for Approximate ComputingFront End
AP4VL19High-Speed Area-EfÞcient VLSI Architecture of Three-Operand Binary AdderFront End
AP4VL20Design of 4:2 Compressor for Parallel Distributed Arithmetic FIR FilterFront End
AP4VL21PERFORMANCE ANALYSIS OF PARALLEL PREFIX ADDER FOR DATAPATH VLSI DESIGNFront End
AP4VL22Approximate Reverse Carry Propagate Adder for Energy-Efficient DSP ApplicationsFront End
AP4VL23Architecture Optimization and Performance Comparison of Nonce-Misuse-Resistant Authenticated Encryption AlgorithmsFront End
AP4VL24TOSAM:AnEnergy-EfficientTruncation-andRounding-BasedScalableApproximate MultiplierFront End
AP4VL25Design And Analysis Of Approximate Redundant Binary Multipliers.Front End
AP4VL26Rounding Technique Analysis Of Power-Area & Energy Efficient Approximate Multiplier DesignFront End
AP4VL27A Combined Arithmetic-High-Level Synthesis Solution to Deploy Partial Carry-Save Radix-8 Booth Multipliers in Datapath.Front End
AP4VL28Low Power High Accuracy Approximate Multiplier Using Approximate High Order Compressors.Front End
AP4VL29Efficient Modular Adder Designs Based on Thermometer & One-Hot EncodingFront End
AP4VL30Error Detection And Correction In SRAM Emulated TCAMsFront End
AP4VL31Efficient Design For Fixed Width Adder TreeFront End
AP4VL32Area ÐTime Efficient Streaming Architecture For Architecture For FAST And BRIEF DetectorFront End
AP4VL33Hard Ware Efficient Post Processing Architecture For True Random Number GeneratorsFront End
AP4VL34A Two Speed Radix -4 Serial ÐParallel MultiplierFront End
AP4VL35Low power approximate unsigned multipliers with configurable error recoveryFront End
AP4VL36Energy Quality Scalable Adders Based On Non Zeroing Bit TruncationFront End
AP4VL37Double MAC On A DSP Boosting The Performance Of Convolutional Neural Networks On FPGASFront End
AP4VL38A Low-Power Parallel Architecture for Linear Feedback Shift RegistersFront End
AP4VL39Ultra-low-voltage GDI-based hybrid full adder design for area and energy-efficient computing systemsBack End
AP4VL40Design Of Area Efficient And Low Power 4-Bit Multiplier Based On Full- swing GDI techniqueBack End
AP4VL41Multistage Linear Feedback Shift Register Counters With Reduced Decoding Logic in 130-nm CMOS for Large-Scale Array ApplicationsBack End
AP4VL42Low-Power Near-Threshold 10T SRAM Bit Cells With Enhanced Data-Independent Read Port Leakage for Array Augmentation in 32-nm CMOSBack End
AP4VL43Column selection enabled 10 T SRAM utilizing shared diff VDD WRITE and dropped VDD read for FFT on real data.Back End
AP4VL44Cell-state-distribution Ðassisted threshold voltage detector for NAND flash memoryBack End
AP4VL45Efficient VLSI Implementation of a Sequential Finite Field Multiplier Using Reordered Normal Basis in Domino LogicBack End
AP4VL46An Approach to LUT Based Multiplier for Short Word Length DSP SystemsFront End
AP4VL47Novel High speed Vedic Multiplier proposal incorporating Adder based on Quaternary Signed Digit number systemFront End
AP4VL48FPGA Implementation of an Improved Watchdog Timer for Safety-critical ApplicationsFront End
AP4VL49Unbiased Rounding for HUB Floating-point AdditionFront End
AP4VL50A Low-Power Yet High-Speed Configurable Adder for Approximate ComputingFront End
AP4VL51A Low-Power High-Speed Accuracy-Controllable Approximate Multiplier DesignFront End
AP4VL52The Design and Implementation of Multi Ð Precision Floating Point Arithmetic Unit Based on FPGAFront End
AP4VL53Extending 3-bit Burst Error-Correction Codes With Quadruple Adjacent Error CorrectionFront End
AP4VL54Efficient Modular Adders based on Reversible CircuitsFront End
AP4VL55MAES: Modified Advanced Encryption Standard for Resource Constraint EnvironmentsFront End
AP4VL56Chip Design for Turbo Encoder Module for In-Vehicle SystemFront End
AP4VL57Low-Power and Fast Full Adder by Exploring New XOR and XNOR GatesBack End
AP4VL58Low Power 4_4 Bit Multiplier Design using Dadda Algorithm and Optimized Full AdderBack End
AP4VL59Low Leakage Fully Half-Select-Free Robust SRAM Cells with BTI Reliability AnalysisBack End
AP4VL60Improved 64-bit Radix-16 Booth Multiplier Based on Partial Product Array Height ReductionFront End
AP4VL61Clock-Gating of Streaming Applications for Energy Efficient Implementations on FPGAsFront End
AP4VL62An Improved DCM-Based Tunable True Random Number Generator for Xilinx FPGAFront End
AP4VL63RoBA Multiplier: A Rounding-Based Approximate Multiplier for High-Speed yet Energy-Efficient Digital Signal ProcessingFront End
AP4VL64DLAU: A Scalable Deep Learning Accelerator Unit on FPGAFront End
AP4VL65Overloaded CDMA Crossbar for Network-On-ChipFront End
AP4VL66Design of Power and Area Efficient Approximate MultipliersFront End
AP4VL67Scalable Approach for Power Droop Reduction During Scan-Based Logic BISTFront End
AP4VL68Design of Low-Power High-Performance 2-4 and 4-16 Mixed-Logic Line Decoders.Back End
AP4VL69Performance Analysis of a Low-Power High-Speed Hybrid 1-bit Full Adder CircuitBack End
AP4VL7012T Memory Cell for Aerospace Applications in Nano scale CMOS TechnologyBack End
AP4VL71Pre-Encoded Multipliers Based on Non-Redundant Radix-4 Signed-Digit EncodingFront End
AP4VL72Flexible DSP Accelerator Architecture Exploiting Carry-Save ArithmeticFront End
AP4VL73Low-Cost High-Performance VLSI Architecture for Montgomery Modular MultiplicationFront End
AP4VL74A High-Speed FPGA Implementation of an RSD-Based ECC ProcessorFront End
AP4VL75Hybrid LUT/Multiplexer FPGA Logic ArchitecturesFront End
AP4VL76In-Field Test for Permanent Faults in FIFO Buffers of NOC RoutersFront End

Contact Us

Have questions or need help? Use the form to reach out and we will be in touch with you as quickly as possible.

WhatsApp
1000+ IEEE Projects

Offering more than 120 domains in all branches with world class projects

Expert Teachers

Having a team of highly qualified trainers having 5+ years experience

Unlimited Access

All the Projects content and videos available in Ameerpet portal