Abstract:
Image/video processing and machine learning use multiplication. FPGA DSP blocks are high-performance multipliers. These multipliers can cause routing delays and are limited in number and location on FPGAs. They may be inefficient for smaller bit-width multiplications. FPGA vendors offer multiplication-optimized soft IP cores. This work suggests that FPGA soft multiplier IP cores need better designs to achieve high performance and resource efficiency. We present generic area-optimized, low-latency accurate, and approximate softcore multiplier architectures that use FPGA lookup table (LUT) structures and fast-carry chains to reduce multiplier critical path delay (CPD) and resource utilization. Our unsigned and signed accurate architecture reduces LUT utilization by 25% and 53% for different multiplier sizes compared to Xilinx multiplier LogiCORE IP. Compared to the LogiCORE IP, our unsigned approximate multiplier architectures can reduce CPD by up to 51% without affecting output accuracy. We tested the multiplier architecture in image and video accelerators for area and performance gains. Our open-source library of accurate and approximate multipliers at https://cfaed.tu-dresden.de/pd-downloads supports further research and development, reproducible research, and a new FPGA community research direction.
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